FIG. 8 is a block diagram showing a prior art high frequency DPDT switch. FIG. 9 is an enlarged view showing detail of an FET part of the signal switch of FIG. 8.
In FIG. 8, reference numerals 2 and 3 designate a first input signal line I.sub.1 and a second input signal line I.sub.2 which are disposed to receive a first signal and a second signal input from the left and the right edge of the DPDT switch respectively. Numerals 4 and 5 designate a first output signal line O.sub.1 and a second output signal line O.sub.2 which are disposed to output either of the first and the second signals from the upper edge of the switch and the other of the first and the second signals from the lower edge of the switch, respectively, perpendicular to the input signal lines 2 and 3. A first FET 50 is arranged to output a signal from the first input signal line I.sub.1 to the first output signal line O.sub.1 or to cut off its output. A second FET 51 is arranged to output a signal from the first input signal line I.sub.1 to the second output signal line O.sub.2 or to cut off its output. A third FET 52 is arranged to output a signal from the second input signal line I.sub.2 to the first output signal line O.sub.1 or to cut off its output. A fourth FET 53 is arranged to output a signal from the second input signal line I.sub.2 to the second output signal line O.sub.2 or to cut off its output. Numerals 6a and 7a designate a first and a second control signal line G.sub.1 and G.sub.2, respectively, which are disposed in parallel with the input signal line 2 to control "on" or "off" switching of the first and the second FETs 50 and 51. Numerals 7b and 6b designate a second and a first control signal line G.sub.2 and G.sub.1, respectively, which are disposed in parallel with the input signal line 3 to control "on" or "off" switching of the third and the fourth FET switch 52 and 53. Numeral 100 designates a signal switch (high frequency DPD switch) comprising the above described elements.
In FIG. 9 showing details of an FET that is part of the signal switch, numeral 8 designates an active layer of the first FET 50 formed on a surface of a semiconductor substrate. An input electrode I 17 of the FET 50 comprises its main electrode part 17a formed on the active layer 8 and its line connecting part 17b formed integrally with the main electrode part 17a. An output electrode O 18 of the FET 50 comprises its main electrode part 18a formed on the active layer 8 and its line connecting part 18b formed integrally with the main electrode part 18a. A control electrode G 19 of the FET comprises its finger part 19a formed between the main electrode parts 17a and 18a of both electrodes on the active layer 8 and its lead part 19b formed extending from the finger part 19a.
Here, the detailed structures of the first to the fourth FETs 51 to 53 are all the same and when constituting the high frequency DPDT switch, the directions of arrangement of the FETs should be appropriately chosen to enable connections with the input and output lines.
A description is given of the operation.
In the FET switch of FIG. 9, when an ON voltage, for example, 0V is applied to the control electrode 19, a high frequency signal input to the input electrode 17 flows through the active layer 8 to the output electrode 18, resulting in the switch being is the "on" state. On the other hand, when an OFF voltage, for example, -5V is applied to the control electrode 19, the input signal cannot flow to the output electrode 18 due to a depletion layer generated in the active layer 8, resulting in the switch being with "off" state. The signal switches 50 to 53 each comprising an FET operate to switch the high frequency signal, by utilizing these two states of the FET. The DPDT switch of FIG. 8 switches the high frequency signals between the two input signal lines I.sub.1 and I.sub.2 and the two output signal lines O.sub.1 and O.sub.2 by employing four FETs.
Now, in FIG. 8, the signal switch FETs 50 and 53, whose control electrodes 19 are connected with the first control line 6a and 6b, respectively, are connected between the first input signal line 2 and the first output signal line 4 and between the second input line 3 and the second output line 5, respectively. The signal switch FETs 51 and 52, whose control electrodes 19 are connected with the second control line 7a and 7b, respectively, are connected between the first input signal line 2 and the second output signal line 5 and between the second input signal line 3 and the first output signal line 4, respectively. When mutually complementary ON/OFF voltages are applied to the first control signal line 6 and the second control signal line 7 respectively, the high frequency first and second input signals received at the first input signal line 2 and the second input signal line 3 are switched between a state where they are output to the first output signal line 4 and the second output signal line 5, respectively, and a state where they are output to the second output signal line 5 and the first output signal line 4, respectively, without interferring with each other in both states.
The above described operation makes it possible to receive the two input signals at the first input signal line 2 and the second input signal line 3 and output respective signals switched between the output paths of the first output signal, line 4 and the second output signal line 5, without interferring with each other.
In the prior art high frequency DPDT switch device constituted as described above, it is necessary to employ at least four FET switches. In addition, because the respective FET switches require input and output electrodes having a certain area in order to enable transmission and cutting off of respective signals, many input and output electrodes have to be disposed in the vicinity of the active layer of the respective FET switches, resulting in the DPDT switch unfavorably occupying a large area on a wafer. Further, it is required to provide output line connecting parts 4a and 5a for connecting the output lines of FET switches 50 and 52 and the output lines of FET switches 51 and 53, respectively, to constitute the output lines 4 and 5, respectively. Also, it is required to make the direction of arrangement of the input line and that of the output line of the DPDT switch perpendicular to each other in view of the structure of the FET switch.